1. Field of the Invention
The present invention relates to direct digital frequency synthesis.
2. State of the Art
Direct digital frequency synthesis (DDFS) consists of generating a digital representation of a desired signal, using logic circuitry and/or a digital computer, and then converting the digital representation to an analog waveform using a digital-to-analog converter (DAC). Such systems can be compact, low power, and can provide very fine frequency resolution with virtually instantaneous switching of frequencies.
A known DDFS system is shown in FIG. 1. A digital modulation signal is input to DDS accumulator logic, the output of which indexes into a read-only memory (ROM). An output signal of the ROM is converted to an analog signal by a DAC. An output signal of the DAC may be smoothed using a filter (not shown) to produce a periodic (e.g., sinusoidal) signal. The DDFS of FIG. 1 is exemplified by U.S. Pat. No. 4,746,880, incorporated herein by reference.
Other DDFS variations are shown in FIG. 2, FIG. 3 and FIG. 4. In FIG. 2, the DDFS of FIG. 1 is incorporated into a conventional PLL structure including a phase/frequency detector (PFD), an analog loop filter and a voltage controlled oscillator (VCO). In FIG. 3, the ROM and the DAC of FIG. 2 are omitted, and the most significant bit (MSB) from the DDS block is input directly to the PFD. In FIG. 4, an output signal of the DDS block is filtered using a direct time filter as described in U.S. Pat. No. 5,247,469, incorporated herein by reference.
One of the challenges of DDFS has been to generate a clean, precisely-modulated waveform. Because of limited time resolution and edge misalignment, spurious output signal transitions ("spurs") occur.
Precision modulation is also a problem in conventional analog frequency synthesizers using a PLL. The problem occurs that the PLL treats signal modulation as drift and attempts to cancel the modulation. Circuit arrangements devised in an attempt to overcome this problem are shown in FIG. 5 and FIG. 6. In FIG. 5, a summing node is provided following the loop filter to which a modulation signal is applied. Details of the summing node are illustrated in exploded view. In FIG. 6, showing the Ewart modulator, a resistive divider network is inserted into the ground reference of the loop filter, and a modulation signal is applied to the resistive divider network as shown. In effect, the ground reference of the loop filter is shifted by the modulation signal, resulting in an output signal of the loop filter being shifted by the amount of the modulation. In FIG. 7, a modulation signal is capacitively coupled to a node of the loop filter circuit. The foregoing circuit arrangements do not enjoy the benefits of DDS.
There remains a need for a synthesizer having the benefits of DDS but that is capable of generating a clean, precisely-modulated waveform.